Electro-Static Discharge (ESD) protection has been one of the important issues in the art of preparation of thin film transistor liquid crystal displays (TFT-LCDs). The idea of ESD protection has been generated in the following situations. When a series of process steps (e.g. dry etching) are performed on the surface of a display substrate, quite a few electrostatic charges will accumulate on the substrate, and discharge randomly when this accumulation reaches a certain level. As a result, some pixel structures will be destroyed, thus leading to display defects and even complete damage to the display.
In the prior art, five photomasks are required to form a TFT array substrate. As illustrated in FIG. 1, the substrate is divided into a display area and a periphery area, wherein the display area includes Section I as a TFT and Section II as a storage capacitor. In preparing the array substrate, at the outset, a first metal layer is formed on the substrate and then patterned by means of a first photomask, thus forming a gate 11A in Section I and a bottom electrode (an electrode of the storage capacitor) 11B in Section II. Next, an insulation layer 12 is formed and then patterned by means of a second photomask, so as to form a channel layer 13 and an ohmic contact layer 14 in Section I. Afterwards, a second metal layer is formed and then patterned using a third photomask to form a drain 15, and the ohmic contact layer 14 is partially etched to expose the channel layer 13. A protection layer 17 is subsequently formed on the above structure and then patterned using a fourth photomask, forming a via hole and thus partially exposing the drain 15 of the TFT. Formation and then patterning of a conductive layer then follows by means of a fifth photomask, so as to form a patterned conductive layer 18 as a top electrode of Section II and as a pixel electrode, which is electrically connected to the drain 15 through the via hole. The structure as shown in FIG. 1 is thus formed through the above steps.
It can be known from the above process steps that the gate line and the data line in the array substrate are generally both single metals. Moreover, the data line constitutes the third layer in the entire process but the second layer in formation of the metal layers. In the fourth step, i.e., the step of etching the via hole, a PV layer is first etched away. As a result, the metal layer where the data line is located will be exposed to a dry plasma. While the insulation layer is constantly being etched, the plasma will continuously bombard the metal layer where the data line is located. Therefore, electrostatic charges constantly accumulate on the metal layer, which would easily lead to the phenomenon of ESD, and even electrostatic breakdown in severe situations, thus resulting in scrap of the array substrate.
Consequently, a solution is in urgent need to lower the risk of occurrence of electrostatic breakdown in the process of etching the via hole.